Lightweight TCP/IP (lwIP) Stack
详情介绍
概述
优势和特点
- Telephone tones tested: Dial, Ring, Busy, Call waiting and Caller ID alert signal
- Configurations supported: Error in tone frequencies in % and relative power level adjust
- Test Vector Testing: Partially compliant with E.180/Q.35 tone specifications
- Error Codes: Reports up to 8 unique high level error codes, such as tone generation in progress, configuration not supported
- Max no. of frequency combination supported: Currently tested for up to 3 frequencies. Can be extended
- Max no. of cadences supported: Currently tested for 4 cadences. Can be extended
- Conformance to Standard: Partial conformance to E.180/Q.35
- Target Processor: This software module supports the BF51x, BF52x, BF53x, BF561 processor families on VisualDSP++ 5.0 Update 6
- Demonstrations are available for the BF518, BF527, BF533, and BF561 EZ-KIT Lites
- Release format: Object code module with C source wrapper
- Input format: Frequency, Cadence and the power level required
- Output buffer samples per block: User-configurable and tested for 16 samples (2ms) to any length required
- Framework dependencies: None
- Output format: 16-bit PCM samples
- Sample Rate: 8000Hz
- Multi-channel: Supported (maximum 32 channels). Fully re-entrant and multi-instancing capable
产品详情
The Signal Tone Generator has been highly optimized to run on the Analog Devices’ Blackfin processor family. It is a self-contained software module that is designed to be compliant with the E.180/Q.35 ITU specification for telephone tones. It has been rigorously tested for various frequency combinations and for regions. It contains a standard C-callable API. The code has been implemented using Instruction and Data cache, and has no dependencies on processor peripherals or registers. This makes system integration much easier.
许可
Each module supports the Analog Devices, Inc. (ADI) Blackfin or SHARC Processor family and is a licensed product that is available in object code format. Recipients must sign or accept a license agreement with ADI prior to being shipped or downloading the modules identified in the license agreement.
性能指标
| Code memory (KiB) | Data RAM (KiB) |
Input Buffer (Bytes) |
MIPS Average |
| 28.330 |
31.260 |
40 |
0.4 |
- MIPS above was obtained using various digits/tones for varying output buffer sizes. The MIPS listed in the table are the worst case average MIPS within this calling convention.
- The peak MIPS occurs when the output buffer size is 16 PCM samples in length (2ms tone). There is no variation in MIPS across Blackfin processor variants. All code, data and stack were placed in L1 memory.
- For the optimal memory layout, all code and data used by the module was located in on-chip L1 memory.
- "Data RAM" for one instance, includes Stack, Scratch, Instance/Stage,
- Minimum Input and Output Single Buffers.
- 1 KiB = 1024 Bytes.
- BF518, BF527, BF533, and BF561 supported.
系统要求
- Windows XP Professional SP3 (32-bit only).
- Windows Vista Business/Enterprise/Ultimate SP2 (32-bit only). It is recommended to install the software in a non-UAC-protected location.
- Windows 7 Professional/Enterprise/Ultimate (32 and 64-bit). It is recommended to install the software in a non-UAC-protected location
- Minimum of 2 GHz single core processor, 3.3 GHz dual core is recommended.
- Minimum of 1 GB memory (RAM), 4 GB is recommended.
- Minimum of 2 GB hard disk (HDD) space is required.