| Number of Channels per Chip | 4 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 150@10V|300@5V|100@15V |
| PCB changed | 16 |
| HTS | 8542.39.00.01 |
| Maximum Quiescent Current (uA) | 20 |
| Number of Elements per Chip | 1 |
| ECCN (US) | EAR99 |
| Minimum Operating Temperature (°C) | -55 |
| Maximum Operating Temperature (°C) | 125 |
| Supplier Package | PDIP |
| Maximum High Level Output Current (mA) | -4.2(Min) |
| Latch Mode | Transparent |
| Process Technology | CMOS |
| Absolute Propagation Delay Time (ns) | 500 |
| Propagation Delay Test Condition (pF) | 50 |
| Package Height | 5.08(Max) - 0.51(Min) |
| Polarity | Inverting/Non-Inverting |
| Maximum Operating Supply Voltage (V) | 18 |
| EU RoHS | Compliant |
| Number of Selection Inputs per Element | 0 |
| Typical Quiescent Current (uA) | 0.04 |
| Set/Reset | No |
| Number of Inputs per Chip | 4 |
| Number of Outputs per Chip | 4 |
| Supplier Temperature Grade | Military |
| Package Length | 19.69(Max) |
| Standard Package Name | DIP |
| Maximum Low Level Output Current (mA) | 4.2(Min) |
| Pin Count | 16 |
| Mounting | Through Hole |
| Type | D-Type |
| Number of Output Enables per Element | 0 |
| Number of Input Enables per Element | 2 (CLK, Polarity) |
| Bus Hold | No |
| Lead Shape | Through Hole |
| Part Status | Active |
| Packaging | Tube |
| Typical Operating Supply Voltage (V) | 12|15|5|3.3|9 |
| Logic Family | CD4000 |
| Package Width | 6.6(Max) |
| Minimum Operating Supply Voltage (V) | 3 |
