| Program Memory Type | Flash |
| Maximum Expanded Memory Size | 4GB |
| Data Bus Width (bit) | 32 |
| SPI | 2 |
| Special Features | CAN Controller |
| Supplier Package | TFLGA |
| Instruction Set Architecture | CISC |
| Core Architecture | RX |
| Family Name | RX |
| Maximum Operating Supply Voltage (V) | 3.6 |
| Maximum Clock Rate (MHz) | 100 |
| EU RoHS | Compliant |
| DAC Channels | 2 |
| Standard Package Name | LGA |
| Pin Count | 145 |
| Mounting | Surface Mount |
| USART | 0 |
| CAN | 1 |
| Lead Shape | No Lead |
| Ethernet | 0 |
| Packaging | Tray |
| Program Memory Size | 512KB |
| Typical Operating Supply Voltage (V) | 3.3 |
| Number of DACs | Single |
| Programmability | Yes |
| Data Memory Size | 32KB |
| PCB changed | 145 |
| ECCN (US) | 3A991 |
| DAC Resolution (bit) | 10 |
| Device Core | RX |
| ADC Channels | 4/4/8 |
| Minimum Operating Temperature (°C) | -40 |
| Maximum Operating Temperature (°C) | 85 |
| No. of Timers | 8 |
| Package Height | 1.2(Max) |
| I2C | 2 |
| Interface Type | CAN/I2C/SPI/USB |
| Maximum CPU Frequency (MHz) | 100 |
| Number of ADCs | Triple |
| USB | 1 |
| RAM Size | 96KB |
| UART | 0 |
| ADC Resolution (bit) | 10/12/12 |
| I2S | 0 |
| Package Length | 9 |
| CECC Qualified | No |
| Watchdog | 1 |
| Number of I/Os | 103 |
| Package Width | 9 |
| Minimum Operating Supply Voltage (V) | 2.7 |
