NXP Semiconductors

Central Processing Unit (CPU32) Upward Object Code Compatible New Instructions for controller Applications 32 Bit Architecture Virtual Memory Implementation Loop Mode of Instruction Execution Table Lookup and Interpolate Instruction Improved Exception Handling for Controller Applications Trace on change of flow Hardware breakpoint signal, Background Debugging Mode (BDM) Fully static operation Dedicated Micro-Engine Operating Independently of CPU32 16 Independent Programmable Channels and Pins Any Channel can Perform Any Time Function Each Channel has Six or Eight 16 Bit Parameter Registers Each Timer Function May Be Assigned to More Than One Channel Two Timer Counter Registers with Programmable Prescalers Each Channel Can Be Synchronized to Either or Both Counters Selectable Channel Priority Levels