| Program Memory Type | SRAM |
| Provider Name | Altera/CAST, Inc/Mobiveil, Inc/Eureka Technology Inc/Barco Silex |
| PCB changed | 1152 |
| Logic Elements | 255000 |
| ECCN (US) | 3A001.a.7.a |
| Number of Global Clocks | 16 |
| Operating Supply Voltage (V) | 1.1 |
| Total Number of Block RAM | 48+864+5100 |
| Minimum Operating Temperature (°C) | -40 |
| Maximum Operating Temperature (°C) | 100 |
| Tradename | Stratix |
| Supplier Package | FC-FBGA |
| Number of I/O Banks | 24 |
| Device Logic Units | 255000 |
| Process Technology | 65nm |
| IP Core | RapidIO to AXI Bridge Controller (RAB)|Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|Multi-Channel HD/DCI JPEG 2000 Encoder (BA110)|PowerPC/SH/1960 System Controller |
| Single-Ended I/O Standards | LVCMOS|LVTTL |
| Package Height | 2.9 |
| Family Name | Stratix® III E |
| Maximum Operating Supply Voltage (V) | 1.15 |
| EU RoHS | Compliant with Exemption |
| I/O Voltage (V) | 1.2|1.5|3.3|2.5|1.8 |
| External Memory Interface | DDR3 SDRAM|DDR2 SDRAM|RLDRAM II|QDRII+SRAM |
| Differential I/O Standards | LVPECL|LVDS |
| Device Number of DLLs/PLLs | 12 |
| Number of Multipliers | 768 (18x18) |
| Embedded Memory (Kbit) | 16282 |
| Supplier Temperature Grade | Industrial |
| Package Length | 35 |
| In-System Programmability | No |
| Standard Package Name | BGA |
| Reprogrammability Support | No |
| Pin Count | 1152 |
| Mounting | Surface Mount |
| Lead Shape | Ball |
| Part Status | Active |
| Copy Protection | Yes |
| Opr. Frequency (MHz) | 450 |
| Speed Grade | 4 |
| Package Width | 35 |
| User I/Os | 744 |
| Shift Registers | Utilize Memory |
| Programmability | No |
| Minimum Operating Supply Voltage (V) | 1.05 |
