| Fabrication Technology | 28nm |
| Program Memory Type | SRAM |
| Provider Name | Altera/Barco Silex/Mobiveil, Inc |
| Taxonomy | Programmable Devices » Programmable Logic Devices » FPGA |
| Logic Elements | 695000 |
| Package Width (mm) | 40 |
| PCIe | 4 |
| Operating Supply Voltage (V) | 0.85 |
| Dedicated DSP | 1963 |
| Minimum Operating Temperature (°C) | 0 |
| Maximum Operating Temperature (°C) | 85 |
| Supplier Package | FC-FBGA |
| Device Logic Units | 695000 |
| Single-Ended I/O Standards | LVTTL|LVCMOS |
| IP Core | Triple Speed Ethernet with 1588|Sub-frame Latency JPEG 2000 Encoder (BA130)|DDR4/3, LPDDR2/3 Multip |
| Screening Level | Commercial |
| Family Name | Stratix® V GS |
| EMACs | 2 |
| Maximum Operating Supply Voltage (V) | 0.88 |
| Package Height (mm) | 3.2 |
| EU RoHS | Compliant |
| External Memory Interface | DDR2 SDRAM|DDR3 SDRAM|RLDRAM II|RLDRAM III|QDRII+SRAM |
| Main Family | Stratix |
| Differential I/O Standards | LVPECL|LVDS|HCSL |
| Device Number of DLLs/PLLs | 28 |
| Number of Multipliers | 3926 (18x18) |
| Embedded Memory | 51200 |
| Standard Package Name | BGA |
| PCB | 1517 |
| Pin Count | 1517 |
| Mounting | Surface Mount |
| Package Length (mm) | 40 |
| Lead Shape | Ball |
| Number of Registers | 1050000 |
| User I/Os | 696 |
