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描述:† The input-to-output differential across the regulator should provide for some margin against regulator operation at the maximum dropout (for a particular current value). This margin is needed to account for tolerances in both the input voltage (lower limit) and the output voltage (upper limit). The absolute minimum VIN for a desired maximum output current can be calculated by the following: VIN(min) = VOUT(max) + VDO(max @ rated current)
描述:Notes: 1. PD indicates an internal pull-down and PU indicates an internal pull-up. 2. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (<0.2). If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces. 3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF[1:0] = LL. 4. Permissible output division ratios connected to FB. The frequency of the REF input will be FNOM/N when the part is configured for frequency multiplication by using an undivided output for FB and setting DS[1:0] to N (N = 1-6, 8, 10, 12).
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描述:MICROCIRCUIT,DIGITAL
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